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Showing results 1 to 4 of 4

1
FBD 및 LD로 구현된 PLC 프로그램의 Verilog 변환을 통한 정형검증 = Formal verification of PLC programs in FBD and LD via verilog translationlink

김병완; Kim, Byong-Wan; et al, 한국과학기술원, 2009

2
FBDVerifier: Interactive and Visual Analysis of Counter-example in Formal Verification of Function Block Diagram

Jee, Eunk Young; Jeon, Seungjae; Cha, Sungdeok; Koh, Kwangyong; Yoo, Junbeom; Park, Geeyong; Seong, Poong-Hyun, JOURNAL OF RESEARCH AND PRACTICE IN INFORMATION TECHNOLOGY, v.42, no.3, pp.171 - 188, 2010-08

3
Formal verification of memory interface in network processors = 네트워크 프로세서의 메모리 인터페이스의 형식 검증link

Kim, Sang-Ho; 김상호; et al, 한국과학기술원, 2003

4
STATE TOKEN PETRI NET MODELING METHOD FOR FORMAL VERIFICATION OF COMPUTERIZED PROCEDURE INCLUDING OPERATOR'S INTERRUPTIONS OF PROCEDURE EXECUTION FLOW

Kim, Yun Goo; Seong, Poong-Hyun, NUCLEAR ENGINEERING AND TECHNOLOGY, v.44, no.8, pp.929 - 938, 2012-12

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