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Showing results 1361 to 1380 of 109491
| A 13.56MHz receiver SoC for multi-standard RFID reader Seo, Min-Woo; Choi, Yong-Chang; Kim, Young-Han; Yoo, Hyung-Joun, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, IEEE, 2008-12-09 |
| A 13.56MHz RFID transceiver SoC for multi-standard reader Seo, M. W.; Choi, Y. C.; Kim, Y. H.; Yoo, Hyung Joun, 2009 IEEE Radio and Wireless Symposium, RWS 2009, pp.75 - 78, IEEE, 2009-01-18 |
| A 13.56MHz RFID transceiver SoC for multi-standard reader Seo, Min-Woo; Choi, Yong-Chang; Kim, Young-Han; Yoo, Hyung-Joun, 2009 IEEE Radio and Wireless Symposium, RWS 2009, pp.75 - 78, IEEE, 2009-01-19 |
| A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory Lee, Juhyoung; Kim, , Jihoon; Jo,Wooyoung; Kim, Sangyeob; Kim, Sangjin; Lee,Jinsu; Yoo, HoiJun, 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Institute of Electrical and Electronics Engineers Inc., 2021-06 |
| A 130V Triboelectric Energy-Harvesting Interface in .18m BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique Lee, Jiho; Lee, Sang-Han; Kang, Gyeong-Gu; Kim, JaeHyun; Cho, Gyu-Hyeong; Kim, Hyun-Sik, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.474 - 476, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation Choi, Edward; Choi, Injun; Jeon, Chanhee; Yun, Gichan; Yi, Donghyeon; Ha, Sohmyung; Chang, Ik-Joon; et al, 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022, Institute of Electrical and Electronics Engineers Inc., 2022-04 |
| A 13GHZ CMOS distributed oscillator using MEMS coupled transmission lines for low phase noise Park E.-C.; Yoon E., Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement, v.47, pp.244 - 245, 2003-02-15 |
| A 14 GHz non-contact radar system for long range heart rate detection Lee, Jee Hoon; Park, Seong Ook, 2013 International Symposium on Antenna and Propagation, SOUTHEAST UNIVERSITY,IEICE,IEEE, 2013-10-23 |
| A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fs rms integrated jitter in 0.13μm CMOS Park, Dongmin; Cho, SeongHwan, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.344 - 346, IEEE, 2012-02-22 |
| A 141 mu W Sensor SoC on OLED/OPD Substrate for SpO(2)/ExG Monitoring Sticker Yoo, Hoi Jun; Lee, Yongsu; Lee, Hyunwoo; Jang, Jaeeun; Lee, Jihee; Kim, Minseo; Lee, Jaehyuk; et al, IEEE International Solid-State Circuits (ISSCC), pp.384 - 385, IEEE, 2016-02 |
| A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices Han, Donghyeon; LEE, Jinsu; Lee, Jinmook; Choi, Sungpill; Yoo, Hoi-Jun, IEEE International Symposium on Circuits & Systems, IEEE International Symposium on Circuits & Systems, 2018-05 |
| A 144MHz integrated resonant regulating rectifier with hybrid pulse modulation Kim, Chul; Ha, Sohmyung; Park, Jiwoong; Akinin, Abraham; Mercier, Patrick P.; Cauwenberghs, Gert, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C284 - C285, Institute of Electrical and Electronics Engineers Inc., 2015-06 |
| A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator Yoon, Kye-Seok; Hong, Sung-Wan; Lee, Sang-Han; Choi, Sung-Won; Cho, Gyu-Hyeong, 31st Symposium on VLSI Circuits, pp.C202 - C203, IEEE, 2017-06 |
| A 145W 88 parallel multiplier based on optimized bypassing architecture Hong, S.; Roh, T.; Yoo, Hoi-Jun, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1175 - 1178, IEEE, 2011-05-15 |
| A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping Kim, Sangyeob; Yoo, Hoi-Jun; LEE, JUHYOUNG; Kang, Sanghoon; Lee, Jinmook, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 |
| A 148fsrms Integrated Noise 4MHz Bandwidth All-Digital Second-Order ΔΣ Time-to-Digital Converter Using Gated Switched-Ring Oscillator Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwan, 2013 IEEE Custom Integrated Circuits Conference - CICC, pp.1 - 4, IEEE, 2013-09-25 |
| A 14b-linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S.; Song, B.-S.; Cho, G.-H.; Bacrania, K., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.464 - 0, 2003-02-15 |
| A 15.2 TOPS/W CNN accelerator with similar feature skipping for face recognition in mobile devices Kim, Sangyeob; Lee, Juhyoung; Kang, Sanghoon; Lee, Jinsu; Yoo, Hoi-Jun, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-05 |
| A 150MHz 8-Banks 256M Synchronous DRAM with the Wave Pipelining Method Yoo, Hoi-Jun, 95 IEEE Int. Solid State Circuit Conf., 1995 |
| A 152mW mobile multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG Woo, J.-H.; Sohn, J.-H.; Kim, H.; Jeong, J.; Jeong, E.; Lee, S.J.; Yoo, Hoi-Jun, 2007 Symposium on VLSI Circuits, VLSIC, pp.220 - 221, 123, 2007-06-14 |
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