Browse by Type Conference
Showing results 1281 to 1300 of 109477
| A 1.25 Gb/s High Sensitive Peak Detector in Optical Burst-Mode Receiver Using a 0.18um CMOS Technology Seo, J.-W.; Han, S.; Lee, S.-G.; Lee, Man Seop; Yoo, T.W., 2003 International Conference on Communication Technology, ICCT 2003, v.1, pp.644 - 646, 2003-04-09 |
| A 1.25Gbit/s AC-Coupled Burst-Mode Receiver for Ethernet PON and Its Deomonstration of Experimental Optical Packet Transmission Lee, Man Seop, OECC/COIN 2004, 2004-07 |
| A 1.25V Direct Conversion CMOS Transmitter Front- End for 900 MHz ZigBee Applications Lee, Sang-Gug, IEEE Midwest International Conference on Circuit And System, pp.0 - 0, 2003-12-01 |
| A 1.2Mpixels/s/mW 3-D rendering processor for portable multimedia application Woo, J.-H.; Lee, M.-W.; Kim, H.; Sohn, J.-H.; Yoo, Hoi-Jun, IEEE Asian Solid-State Circuits Conference, ASSCC 2005, pp.297 - 300, 2005-11-01 |
| A 1.2mW on-line learning mixed mode intelligent inference engine for robust object recognition Oh, Jinwook; Lee, Seungjin; Kim, Minsu; Kwon, Joonsoo; Park, Junyoung; Kim, Joo-Young; Yoo, Hoi-Jun, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, pp.17 - 18, Institute of Electrical and Electronics Engineers Inc., 2010-06-16 |
| A 1.3 pJ/bit Energy-Efficient Ultra-Low Power On-off mode Oscillator Using an InP-based Quantum-effect Tunneling Device Lee, Jooseok; Lee, Jongwon; Park, Jaehong; Kim, Maengkyu; Yang, Kyounghoon, IEEE International Conference on InP and Related Materials, IEEE, 2012-08 |
| A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture Han, Donghyeon; Lee, Jinsu; Lee, Jinmook; Yoo, Hoi-Jun, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, pp.C304 - C305, Institute of Electrical and Electronics Engineers Inc., 2019-06 |
| A 1.3pJ/b inductive coupling transceiver with adaptive gain control for Cm-range 50Mbps data communication Lee, S.; Yoo, J.; Song, K.; Yoo, Hoi-Jun, 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, pp.297 - 300, 2009-11-16 |
| A 1.41mW On-chip/Off-chip Hybrid Transposition Table for Low-power Robust Deep Tree Search in Artifiicial Intelligence SoCs Shin, Dongjoo; Kim, Youchang; Yoo, Hoi-Jun, 30th IEEE International System on Chip Conference, SOCC 2017, pp.138 - 142, IEEE Computer Society, 2017-09 |
| A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoT Systems Sim, Jae Hyeong; Park, Jun Seok; Kim, Min Hye; Bae, Dong Myung; Choi, Yeong Jae; Kim, Lee Sup, 2016 IEEE ISSCC, IEEE solid-state circuits society, 2016-02-02 |
| A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system Kim, Minseo; Kim, Hyunki; Jang, Jaeeun; Lee, Jihee; Lee, Jaehyuk; Lee, Jiwon; Lee, Kyoung-Rog; et al, 64th IEEE International Solid-State Circuits Conference (ISSCC), pp.354, IEEE, 2017-02 |
| A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOS Lee, Junghyup; George, Arup; Je, Minkyu, IEEE International Solid-State Circuits Conference (ISSCC), IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016-02-01 |
| A 1.5-GHz 63dB SNR 20mW direct RF sampling bandpass VCO-based ADC in 65nm CMOS Yoon, Y.-G.; Cho, SeongHwan, 2009 Symposium on VLSI Circuits, pp.270 - 271, 123, 2009-06-16 |
| A 1.55ns 0.015 mm2 64-bit quad number comparator Kim, M.; Kim, J.-Y.; Yoo, Hoi-Jun, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp.283 - 286, 2009-04-28 |
| A 1.5nJ/pixel Super-Resolution Enhanced FAST Corner Detection Processor for High Accuracy AR Yoo, Hoi-Jun; Park, Seongwook; Kim, Gyeonghoon; Park, Junyoung, European Solid State Circuits Conference (ESSCIRC), pp.191 - 194, IEEE, 2014-09-23 |
| A 1.5um laser package frequency-locked with a novel miniature discharge lamp Chung, Yun Chur; Derosier, RM; Presby, HM; Burrus, CA; Akai, Y; Masuda, N, Optical Fiber Communication Conference, 1992 |
| A 1.5V, 140uA CMOS ultra-low power common-gate LNA Jeong C.J.; Qu W.; Sun Y.; Yoon D.Y.; Han S.K.; Lee, Sang-Gug, 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011, IEEE, 2011-06-05 |
| A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme Kim, Y.; Sung, K.-H.; Kim, Lee-Sup, 2002 IEEE International Symposium on Circuits and Systems, pp.I-461 - I-464, IEEE, 2002-05-26 |
| A 1.7-GHz GaN MMIC Doherty Power Amplifier using an Adaptive Bias Circuit with a Quadrature Coupler Lee, Seungkyeong; Lee, Sangmin; Hong, Songcheol, 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2017), IEEE, 2017-09-01 |
| A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS Lee, J.; Kim, J.; Cho, SeongHwan, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010, pp.293 - 296, IEEE, 2010-05-23 |
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