Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

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The low-power/high-speed performance of current-mode logic (CML) D flip-flops based on negative-differential-re si stance (NDR) devices is presented. The device count used in the fabricated circuit has been significantly reduced by using the NDR-based D flip-flop topology, leading to enhanced low-power/high-speed performance. The operation of the fabricated NDR-based CML D flip-flop has been confirmed to 36 Gb/s, which is the highest speed among NDR-based differential-mode D flip-flops reported to date. The power consumption of the D flip-flop core circuit was measured to be as low as 20 mW at a power supply voltage of -3.3 V. In addition, a power-delay product of 0.55 pJ has been obtained from the NDR-based CML D flip-flop, which is the lowest value to the authors' knowledge among the previously reported D flip-flops up to operation speeds in the region of 40 Gb/s.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2008-04
Language
English
Article Type
Article
Keywords

RESONANT-TUNNELING DIODES; TECHNOLOGY; FREQUENCY; OPERATION; ELEMENT; MOBILE; TIME; GHZ

Citation

IET CIRCUITS DEVICES & SYSTEMS, v.2, no.2, pp.281 - 287

ISSN
1751-858X
DOI
10.1049/iet-cds:20070135
URI
http://hdl.handle.net/10203/91897
Appears in Collection
EE-Journal Papers(저널논문)
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