Border-trap characterization in high-kappa strained-si MOSFETs

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In this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 run. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained-Si/Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2007-08
Language
English
Article Type
Article
Keywords

MOS DEVICES; GATE STACK; NOISE; NMOSFETS; DIELECTRICS; QUALITY; IMPACT

Citation

IEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733

ISSN
0741-3106
DOI
10.1109/LED.2007.902086
URI
http://hdl.handle.net/10203/88014
Appears in Collection
EE-Journal Papers(저널논문)
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