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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Journal Papers(저널논문)

Border-trap characterization in high-kappa strained-si MOSFETs

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dc.contributor.authorMaji, Debabratako
dc.contributor.authorDuttagupta, S. P.ko
dc.contributor.authorRao, V. Rarngopalko
dc.contributor.authorYeo, Chia Chingko
dc.contributor.authorCho, Byung Jinko
dc.date.accessioned2013-03-06T18:47:23Z-
dc.date.available2013-03-06T18:47:23Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2007-08-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/88014-
dc.description.abstractIn this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 run. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained-Si/Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectMOS DEVICES-
dc.subjectGATE STACK-
dc.subjectNOISE-
dc.subjectNMOSFETS-
dc.subjectDIELECTRICS-
dc.subjectQUALITY-
dc.subjectIMPACT-
dc.titleBorder-trap characterization in high-kappa strained-si MOSFETs-
dc.typeArticle-
dc.identifier.wosid000248315400021-
dc.identifier.scopusid2-s2.0-34547751876-
dc.type.rimsART-
dc.citation.volume28-
dc.citation.issue8-
dc.citation.beginningpage731-
dc.citation.endingpage733-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.identifier.doi10.1109/LED.2007.902086-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorMaji, Debabrata-
dc.contributor.nonIdAuthorDuttagupta, S. P.-
dc.contributor.nonIdAuthorRao, V. Rarngopal-
dc.contributor.nonIdAuthorYeo, Chia Ching-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorborder traps-
dc.subject.keywordAuthorcharge pumping-
dc.subject.keywordAuthorhysteresis-
dc.subject.keywordAuthorinterface-
dc.subject.keywordAuthortrapping-
dc.subject.keywordAuthorstrained-Si-
dc.subject.keywordAuthor1/f noise-
dc.subject.keywordPlusMOS DEVICES-
dc.subject.keywordPlusGATE STACK-
dc.subject.keywordPlusNOISE-
dc.subject.keywordPlusNMOSFETS-
dc.subject.keywordPlusDIELECTRICS-
dc.subject.keywordPlusQUALITY-
dc.subject.keywordPlusIMPACT-
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