Conforming block inversion for low power memory

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In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline toggling and ultimately contributes to power reduction of the memory.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2002-02
Language
English
Article Type
Article
Keywords

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Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.10, no.1, pp.15 - 19

ISSN
1063-8210
URI
http://hdl.handle.net/10203/83866
Appears in Collection
EE-Journal Papers(저널논문)
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