Conforming block inversion for low power memory

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dc.contributor.authorChang, YSko
dc.contributor.authorKyung, Chong-Minko
dc.date.accessioned2013-03-04T19:37:53Z-
dc.date.available2013-03-04T19:37:53Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2002-02-
dc.identifier.citationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.10, no.1, pp.15 - 19-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://hdl.handle.net/10203/83866-
dc.description.abstractIn this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline toggling and ultimately contributes to power reduction of the memory.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectI/O-
dc.titleConforming block inversion for low power memory-
dc.typeArticle-
dc.identifier.wosid000174317700003-
dc.identifier.scopusid2-s2.0-0036476969-
dc.type.rimsART-
dc.citation.volume10-
dc.citation.issue1-
dc.citation.beginningpage15-
dc.citation.endingpage19-
dc.citation.publicationnameIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorChang, YS-
dc.type.journalArticleArticle-
dc.subject.keywordAuthordynamic logic circuit-
dc.subject.keywordAuthorlow-power design-
dc.subject.keywordAuthorlow-power dissipation-
dc.subject.keywordAuthormemory-
dc.subject.keywordAuthorswitching activity-
dc.subject.keywordPlusI/O-
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