A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique

Abstract

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required, A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-mum CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply, The active die area of the chip with the on-chip data pattern generator is 2.4 mm(2).