A linear programming-based algorithm for floorplanning in VLSI design

In this paper, we consider a floorplanning problem in the physical design of very large scale integration. We focus on the problem of placing a set of blocks (modules) on a chip with the objective of minimizing area of the chip as well as total wire length. The blocks have different areas and their shapes are either fixed (predetermined) or flexible (to be determined). We use the sequence-pair suggested by Murata et al. to represent the topology of nonslicing floorplans and present two methods to obtain a floorplan from a sequence-pair. One is a construction method, and the other is a method based on a linear programming model. The two methods are embedded in simulated annealing algorithms, which are used to find a near optimal floorplan. Results of computational experiments on the Microelectronics Center of North Carolina benchmark examples show that the proposed algorithms work better than existing algorithms.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-05
Language
ENG
Keywords

FLEXIBLE MANUFACTURING SYSTEMS; SLICING FLOORPLANS; FACILITY LAYOUT; AREA MINIMIZATION; UNIFIED APPROACH; OPTIMIZATION; CONSTRAINTS

Citation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.22, no.5, pp.584 - 592

ISSN
0278-0070
URI
http://hdl.handle.net/10203/7744
Appears in Collection
IE-Journal Papers(저널논문)
Files in This Item
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