Dual-Loop Digital PLL for Adaptive Clock Recovery

Publisher
대한전자공학회
Issue Date
1997-12
Language
ENG
Citation

CAD 및 VLSI 설계연구회지, v.6, no.1, pp.131 - 143

URI
http://hdl.handle.net/10203/73192
Appears in Collection
RIMS Journal Papers
Files in This Item
There are no files associated with this item.
  • Hit : 139
  • Download : 0
  • Cited 0 times in thomson ci

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0