A Nano-Structure Memory with SOI Edge Channel and a Nano Dot

Cited 3 time in webofscience Cited 0 time in scopus
  • Hit : 444
  • Download : 0
We fabricated nano structure memory with silicon on insulator (SOI) edge channel and a nano dot. The width of the edge channel was determined by the thickness of the recessed rep-silicon layer of SOI wafer and the size of sidewall nano dot was determined by the reactive ion etching (RIE) etch and E-beam lithography. The memory has the threshold voltage shift of about 1 V for maximum programming voltage of 7 V and showed reasonable retention and endurance characteristics.
Publisher
Japan Soc Applied Physics
Issue Date
1998-12
Language
English
Article Type
Article; Proceedings Paper
Keywords

ROOM-TEMPERATURE OPERATION; SINGLE-ELECTRON MEMORY; GATE

Citation

JAPANESE JOURNAL OF APPLIED PHYSICS, v.37, no.12B, pp.7190 - 7192

ISSN
0021-4922
URI
http://hdl.handle.net/10203/72814
Appears in Collection
RIMS Journal Papers
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 3 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0