Partially Depleted SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the Recessed Channel Region

Abstract

A new SOI NMOSFET with a ''LOCOS-like'' shape self-aligned polgsilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication, Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed, Drain current measured from 0.3 mu m SOI devices with V-T of 0.773 V and T-ox = 7.6 nm is 360 mu A/mu m at V-GS = 3.5 V and V-DS = 2.5 V. Improved breakdown characteristics were obtained and the BVDSS (the drain voltage for 1 nA/mu m of I-D at V-GS = 0 V) of the device with L-eff = 0.3 mu m under the floating body condition was as high as 3.7 V.