100MHz all-digital delay-locked loop for low power application

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An all-digital delay-locked loop (AD-DLL) is proposed for low power application. The AD-DLL saves design time and effort for synthesis. The number of transistors is reduced by 50% by introducing a dual-clock dual-input data flip-flop and a coarse delay time buffer. The lock indicator enables zero jitter.
Publisher
IEE-INST ELEC ENG
Issue Date
1998-09
Language
English
Article Type
Article
Citation

ELECTRONICS LETTERS, v.34, no.18, pp.1739 - 1740

ISSN
0013-5194
DOI
10.1049/el:19981242
URI
http://hdl.handle.net/10203/67775
Appears in Collection
EE-Journal Papers(저널논문)
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