100MHz all-digital delay-locked loop for low power application
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, BS | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2013-02-27T09:33:58Z | - |
| dc.date.available | 2013-02-27T09:33:58Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1998-09 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.34, no.18, pp.1739 - 1740 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/67775 | - |
| dc.description.abstract | An all-digital delay-locked loop (AD-DLL) is proposed for low power application. The AD-DLL saves design time and effort for synthesis. The number of transistors is reduced by 50% by introducing a dual-clock dual-input data flip-flop and a coarse delay time buffer. The lock indicator enables zero jitter. | - |
| dc.language | English | - |
| dc.publisher | IEE-INST ELEC ENG | - |
| dc.title | 100MHz all-digital delay-locked loop for low power application | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000076053500023 | - |
| dc.identifier.scopusid | 2-s2.0-0032480184 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 34 | - |
| dc.citation.issue | 18 | - |
| dc.citation.beginningpage | 1739 | - |
| dc.citation.endingpage | 1740 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.identifier.doi | 10.1049/el:19981242 | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Kim, BS | - |
| dc.type.journalArticle | Article | - |
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