This paper proposes a new standard cell placement procedure based on an efficient global placement strategy called HALO (hierarchical alternating linear ordering), which generates a global 2-D placement of circuit modules by hiearchical application of linear ordering in alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of row assignment, feed-through cell assignment and intrarow cell assignment steps. Experimental results on two benchmark circuits, primary1 and primary2, consisting of 752 and 2907 cells, have shown decreases of the half-perimeter routing lengths by 7% and 24% respectively, compared with the best available results obtained so far. Total CPU time, including the subsequent detailed placement, was less than half that of earlier work.