HALO - AN EFFICIENT GLOBAL PLACEMENT STRATEGY FOR STANDARD CELLS

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dc.contributor.authorYANG, YYko
dc.contributor.authorKyung, Chong-Minko
dc.date.accessioned2013-02-25T23:39:35Z-
dc.date.available2013-02-25T23:39:35Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1992-08-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.11, no.8, pp.1024 - 1031-
dc.identifier.issn0278-0070-
dc.identifier.urihttp://hdl.handle.net/10203/66060-
dc.description.abstractThis paper proposes a new standard cell placement procedure based on an efficient global placement strategy called HALO (hierarchical alternating linear ordering), which generates a global 2-D placement of circuit modules by hiearchical application of linear ordering in alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of row assignment, feed-through cell assignment and intrarow cell assignment steps. Experimental results on two benchmark circuits, primary1 and primary2, consisting of 752 and 2907 cells, have shown decreases of the half-perimeter routing lengths by 7% and 24% respectively, compared with the best available results obtained so far. Total CPU time, including the subsequent detailed placement, was less than half that of earlier work.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectOPTIMIZATION-
dc.titleHALO - AN EFFICIENT GLOBAL PLACEMENT STRATEGY FOR STANDARD CELLS-
dc.typeArticle-
dc.identifier.wosidA1992JG38600008-
dc.identifier.scopusid2-s2.0-0026901315-
dc.type.rimsART-
dc.citation.volume11-
dc.citation.issue8-
dc.citation.beginningpage1024-
dc.citation.endingpage1031-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorYANG, YY-
dc.type.journalArticleArticle-
dc.subject.keywordPlusOPTIMIZATION-
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