Low-power network-on-chip for high-performance SoC design

An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-hip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IN, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 x 5 mm(2) chip containing all the above features is fabricated by 0.18-mu m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2006-02
Language
ENG
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.14, pp.148 - 160

ISSN
1063-8210
DOI
10.1109/TVLSI.2005.863753
URI
http://hdl.handle.net/10203/6296
Appears in Collection
EE-Journal Papers(저널논문)
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