Packet-switched on-chip interconnection network for system-on-chip applications

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Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-mu m CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2005-06
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.52, pp.308 - 312

ISSN
1549-7747
DOI
10.1109/TCSII.2005.848972
URI
http://hdl.handle.net/10203/6290
Appears in Collection
EE-Journal Papers(저널논문)
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