A novel logic concept, Race Logic Architecture (RALA), is proposed. RALA is a new logic operation architecture in that the racing between input variables along the interconnection lines functions as an active logic element instead of logic gates, while the logic gates play a simple passive role. Logic operations of RALA are based on wired-OR that utilizes shared space and serial-AND that utilizes the triggering sequence of input variables. With these two concepts, RALA can implement arbitrary Boolean operations. Various kinds of combinational circuits are simulated and compared with RALA's. RALA shows the best performance in delay time, area, and power product results. A 64-bit carry-look-ahead adder with RALA is fabricated by 0.25-mum CMOS technology to verify its feasibility and functionality. The area of the adder is 800 mum x 150 mum, and the delay time from the clock to Sum31 measured 0.9 ns.