An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

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An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2006-04
Language
ENG
Article Type
Article; Proceedings Paper
Keywords

POWER EMBEDDED MICROPROCESSOR; DYNAMIC VOLTAGE; FREQUENCY MANAGEMENT; SUBSTRATE NOISE; CACHE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, pp.823 - 830

ISSN
0018-9200
URI
http://hdl.handle.net/10203/6250
Appears in Collection
EE-Journal Papers(저널논문)
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