LOWER BOUND OF SAMPLE WORD-LENGTH IN BIT DIGIT SERIAL ARCHITECTURES

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In bit/digit-serial architectures the allowable sample word length is lower-bounded to synchronise the feedback loops (the cycles) correctly. A systematic procedure for finding this lower bound and the critical cycle that achieves the bound are described. From this information a successful schedule can be guaranteed for all cases, which has been difficult using previous approaches.
Publisher
IEE-INST ELEC ENG
Issue Date
1992-01
Language
English
Citation

ELECTRONICS LETTERS, v.28, no.1, pp.60 - 62

ISSN
0013-5194
URI
http://hdl.handle.net/10203/60346
Appears in Collection
EE-Journal Papers(저널논문)
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