LOWER BOUND OF SAMPLE WORD-LENGTH IN BIT DIGIT SERIAL ARCHITECTURES
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | KIM, JY | ko |
| dc.contributor.author | Lee, Hwang Soo | ko |
| dc.date.accessioned | 2013-02-25T05:43:15Z | - |
| dc.date.available | 2013-02-25T05:43:15Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1992-01 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.28, no.1, pp.60 - 62 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/60346 | - |
| dc.description.abstract | In bit/digit-serial architectures the allowable sample word length is lower-bounded to synchronise the feedback loops (the cycles) correctly. A systematic procedure for finding this lower bound and the critical cycle that achieves the bound are described. From this information a successful schedule can be guaranteed for all cases, which has been difficult using previous approaches. | - |
| dc.language | English | - |
| dc.publisher | IEE-INST ELEC ENG | - |
| dc.title | LOWER BOUND OF SAMPLE WORD-LENGTH IN BIT DIGIT SERIAL ARCHITECTURES | - |
| dc.type | Article | - |
| dc.identifier.wosid | A1992HA18400038 | - |
| dc.identifier.scopusid | 2-s2.0-0027107075 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 28 | - |
| dc.citation.issue | 1 | - |
| dc.citation.beginningpage | 60 | - |
| dc.citation.endingpage | 62 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | Lee, Hwang Soo | - |
| dc.contributor.nonIdAuthor | KIM, JY | - |
| dc.subject.keywordAuthor | LARGE-SCALE INTEGRATION | - |
| dc.subject.keywordAuthor | INTEGRATED CIRCUITS | - |
| dc.subject.keywordAuthor | DIGITAL CIRCUITS | - |
| dc.subject.keywordAuthor | ALGORITHMS | - |
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