Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"

In a recent paper, a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang. The proposed flip-flop violates the edge-triggering characteristic. However, the high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2000-06
Language
ENG
Description

IEEE Journal of Solid State Circuits June. 2000.

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.6, pp.919 - 920

ISSN
0018-9200
URI
http://hdl.handle.net/10203/486
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
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