Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sung, KH | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2007-06-13T07:37:41Z | - |
| dc.date.available | 2007-06-13T07:37:41Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2000-06 | - |
| dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.6, pp.919 - 920 | - |
| dc.identifier.issn | 0018-9200 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/486 | - |
| dc.description | IEEE Journal of Solid State Circuits June. 2000. | en |
| dc.description.abstract | In a recent paper, a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang. The proposed flip-flop violates the edge-triggering characteristic. However, the high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler. | - |
| dc.language | English | - |
| dc.language.iso | en_US | en |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler" | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000087549400015 | - |
| dc.identifier.scopusid | 2-s2.0-0033687932 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 35 | - |
| dc.citation.issue | 6 | - |
| dc.citation.beginningpage | 919 | - |
| dc.citation.endingpage | 920 | - |
| dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
| dc.embargo.liftdate | 9999-12-31 | - |
| dc.embargo.terms | 9999-12-31 | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Sung, KH | - |
| dc.type.journalArticle | Letter | - |
| dc.subject.keywordAuthor | edge-triggering | - |
| dc.subject.keywordAuthor | flip-flops | - |
| dc.subject.keywordAuthor | short circuit currents | - |
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