Study on the A/D conversion error due to capacitance error = 정전용량 오차가 아날로그 디지탈 변환오차에 미치는 영향

This purpose of this thesis is the study on the A/D conversion error due to capacitance error. A new approach to track A/D conversion error which is called the ``correlation approach`` is proposed. The study on the kinds of capacitance error says that proper unit capacitor size for 8-bit ADC using the capacitor array is 15 x 15 - 20 x 20 (um x um). It is revealed that the common centroid scheme and the parallel connection of unit capacitors which are proposed to maintain the ratio of capacitance by McCreary, increase the correlation coefficient between capacitors. This result is validated by the measurement of capacitance in Integrated Circuit.
Advisors
Kim, Choong-KiresearcherKyung, Chong-Minresearcher김충기researcher경종민researcher
Publisher
한국과학기술원
Issue Date
1985
Identifier
64672/325007 / 000831293
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1985.2, [ iii, 52 p. ]

URI
http://hdl.handle.net/10203/39731
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=64672&flag=t
Appears in Collection
EE-Theses_Master(석사논문)
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