Study on the A/D conversion error due to capacitance error정전용량 오차가 아날로그 디지탈 변환오차에 미치는 영향

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dc.contributor.advisorKim, Choong-Ki-
dc.contributor.advisorKyung, Chong-Min-
dc.contributor.advisor김충기-
dc.contributor.advisor경종민-
dc.contributor.authorLee, Yun-Tae-
dc.contributor.author이윤태-
dc.date.accessioned2011-12-14T02:23:07Z-
dc.date.available2011-12-14T02:23:07Z-
dc.date.issued1985-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=64672&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/39731-
dc.description학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1985.2, [ iii, 52 p. ]-
dc.description.abstractThis purpose of this thesis is the study on the A/D conversion error due to capacitance error. A new approach to track A/D conversion error which is called the ``correlation approach`` is proposed. The study on the kinds of capacitance error says that proper unit capacitor size for 8-bit ADC using the capacitor array is 15 x 15 - 20 x 20 (um x um). It is revealed that the common centroid scheme and the parallel connection of unit capacitors which are proposed to maintain the ratio of capacitance by McCreary, increase the correlation coefficient between capacitors. This result is validated by the measurement of capacitance in Integrated Circuit.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.titleStudy on the A/D conversion error due to capacitance error-
dc.title.alternative정전용량 오차가 아날로그 디지탈 변환오차에 미치는 영향-
dc.typeThesis(Master)-
dc.identifier.CNRN64672/325007-
dc.description.department한국과학기술원 : 전기 및 전자공학과, -
dc.identifier.uid000831293-
dc.contributor.localauthorKim, Choong-Ki-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.localauthor김충기-
dc.contributor.localauthor경종민-
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EE-Theses_Master(석사논문)
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