Pulse width allocation and clock skew scheduling

Abstract

Pulsed latches, latches driven by a brief clock pulse, offer the convenience of timing verification and optimization as in flip-flop-based circuits, while retaining superior design parameters of latches over flip-flops. But, pulsed latch-based design using a single pulse width has a limitation in reducing its clock period, which can be used for higher frequency or for lower $V_{dd}$. The limitation still exists even when clock skew scheduling is employed, since the amount of skew that can be assigned and realized is practically limited due to process variation. The problem of allocating pulse widths (out of small discrete number of predefined widths) and scheduling clock skews (within prescribed upper bound of skew that can be reliably realized) is formulated, for the first time, for optimizing pulsed latch-based sequential circuits. An algorithm called PWCS_Optimize is proposed to solve the problem; the allocated skews are realized through synthesis of local clock trees between pulse generators and latches, and a global clock tree between a clock source and pulse generators. Experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum achievable clock period for many benchmark circuits and figure of merit of 0.86 on average (1.0 indicates minimum clock period), while cutting area by 11% on average. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.