An unified phase-frequency locking loop by combining PLL, DLL, and Injection Locking

Abstract

An Unified Phase-Frequency Locking Loop by Combining PLL, DLL, and Injection Locking is designed. Depending upon noise conditions of surroundings, either PLL or DLL with injection locking is chosen to be operated. If the jitter of reference clock is little, DLL should be chosen. Otherwise, to filter out the noise, PLL should be chosen. With injection locking, low jitter, low phase noise, short locking time, and wide lock range are achieved. In this work, low jitter characteristics is proved by simulations. Designed circuit is inputted 100MHz reference clock and outputs 400MHz output clock. 4-stage Ring Oscillator is used for voltage-controlled oscillator, and it is shared with PLL and DLL. Specially to guarantee enough delay in DLL, each output stage in delay cells has two optional capacitors. Further, 60dB attenuated reference clock is injected into the input of the first delay cell for injection locking. This locking loop simply combining PLL, DLL and Injection Locking on a one loop is designed in 0.18-μm CMOS technology. Total power consumption is 3.69-mW under 1.5-V power supply.