Implementation of lifting-based discrete wavelet transform processor using look-ahead scheme

Abstract

As demand of high-resolution images, a new compression standard of still images which has better performance than JPEG is announced, JPEG2000. The mainly distinguished feature of the new standard is applying discrete wavelet transform (DWT). Though it helps higher compression, it generally inherits a lot of computation and iteration. The lifting-based DWT recommended in JPEG2000 standard is reduced the complexity of computation, but it still has problems of critical path delay. In previous works, because the lifting-based DWT has a regular architecture of multiplication and addition, pipelining scheme is adopted to reduce the load of computation time. However, pipeline registers occupy large area. This paper resolves a number of the pipeline registers by look-ahead scheme. The proposed architecture remains critical path delay, but has less than half number of registers. The operating frequency is 100MHz, and logic area without memory is 35k gates. The DWT processor is synthesized in SAMSUNG 0.18um and verified on Terasic DE2 FPGA Board.