Low-Area QC-LDPC Decoder Architecture for IEEE 802.16e Applications

Abstract

In the thesis, a quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture, specifically designed for IEEE 802.16e (WiMAX) standard applications, has been proposed. The proposed decoder can support all the code rates and codeword length defined in the standard. In order to achieve the low-area, the decoder utilizes only 4 decoding function units (DFUs), which is the greatest common divisor of the expansion factors specified in the standard. Using small number of DFUs enables to replace the complex flexible permutation network to simple small size cyclic shifter. The decoder divides the check nodes of a layer into 4 subsets and each DFU process one of the subsets sequentially. The memory stores the extrinsic messages in the same manner, so that regardless of the expansion factor of the code, the required messages can be acquired in a single memory access operation. Every memory instance in the decoder is a single port memory which consumes less area and cost compared to two port memory. Read buffers and write buffers ensure there is no memory access contention at the single port memory. In order to reduce the number of memory instances, the extrinsic memory for the 24 column blocks are arranged into 5 memory banks using independent set problem. To ensure that the throughput meets the requirement of the standard, the decoder adopts 4 stages of pipeline structure for the datapath. The synthesized result of the proposed decoder, using 0.18um CMOS technology, shows 49K of logic gate counts and 54,144 bits of memory. The decoder operates at 312.5MHz and the decoding throughput varies from 54Mbps to 116Mbps according to the code’s configuration, which is always greater than the minimum requirement of IEEE 802.16e.