Design and implementation of low-power network-on-chip for application to high-performance system-on-chip design

Abstract

A low-power packet-switched Network-on-Chip (NoC) is designed with hierarchical star topology and implemented in real silicon for possible application to high-performance SoCs. This dissertation presents how to obtain low power consumption in NoC while the whole NoC design process is covered from the architecture decision to the system demonstration. First, a performance and cost oriented topology exploration is performed. The evaluated topologies include not only flat topologies such as a bus, mesh, star and point-to-point but also sixteen hierarchical and heterogeneous topologies. The evaluation method uses technology-independent analytical models with implementation-based physical parameters. Second, the detail network architecture such as switching method, packet synchronization, link serialization, protocol and buffering schemes are analyzed with special emphasis on low power consumption. The implemented chip contains two RISC processors for multiprocessor emulation, two 64kb SRAMs, an on-chip FPGA, an off-chip gateway for interfacing to outer network, three 4kb SRAMs for peripheral logic emulation, 1.6GHz PLL for internal clock generation, and on-chip networks connecting those processing units. On-chip network channel is serialized from 80bits onto 8bits to reduce the network area and complexity of the network. Source-synchronous signaling enables plesiochronous communications between processing units running at different clock frequencies. Low-power consumption is achieved by adopting various techniques such as lower swing signaling on a global link, Mux-Tree based round-robin scheduler in a router, crossbar partial activation, low-energy serial-link coding and clock frequency scaling. The chip consumes less than 160mW and the on-chip network consumes less than 51mW delivering 11.2GB/s aggregated network bandwidth. The power consumption per bandwidth is a ninth of the previous study. The 5x5㎟ chip is fabricated with 0.18μm CMOS process and a system...