(A) system for generating logic level description from geometric description of a VLSI design = VLSI 설계의 기하학적 표현에서 논리적 표현을 생성하는 시스템

This thesis describes a system which generates the logic level description (Boolean expression) from the geometry level description (CIF) of a VLSI design. Logic level descriptions are represented in terms of Boolean expressions and generated from the circuits extracted from CIF description. A number of intellectually interesting algorithms are developed for the conversion of multilevel representations of a VLSI design. The recognizable circuits are polysilicon gate NMOS transistors. This system can provide for valuable information about the correctness of logic implementation before the chip is fabricated and reduce VLSI development period and cost. This system is implemented in about three hundred lines of "C" code and runs on a VAX 11/780 computer under UNIX operating system.
Advisors
Chung, Won-Lyangresearcher정원량researcher
Publisher
한국과학기술원
Issue Date
1986
Identifier
65176/325007 / 000841379
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학과, 1986.2, [ [ii], 31 p. ]

URI
http://hdl.handle.net/10203/33706
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65176&flag=t
Appears in Collection
CS-Theses_Master(석사논문)
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