(A) system for generating logic level description from geometric description of a VLSI design

Abstract

This thesis describes a system which generates the logic level description (Boolean expression) from the geometry level description (CIF) of a VLSI design. Logic level descriptions are represented in terms of Boolean expressions and generated from the circuits extracted from CIF description. A number of intellectually interesting algorithms are developed for the conversion of multilevel representations of a VLSI design. The recognizable circuits are polysilicon gate NMOS transistors. This system can provide for valuable information about the correctness of logic implementation before the chip is fabricated and reduce VLSI development period and cost. This system is implemented in about three hundred lines of "C" code and runs on a VAX 11/780 computer under UNIX operating system.