Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders

Publisher
IEEE
Issue Date
2001-05-06
Language
ENG
Citation

IEEE International Symposium on Circuits and Systems (ISCAS 2001), v.2, pp.693 - 696

ISSN
0271-4310
URI
http://hdl.handle.net/10203/3129
Appears in Collection
EE-Conference Papers(학술회의논문)
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