Address code generation for DSP instruction-set architectures

This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to the address computation of array accesses. The information is used in generating auto-modification addressing operations provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance and reducing code size.
Publisher
ASSOC COMPUTING MACHINERY
Issue Date
2003-07
Language
ENG
Citation

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.8, no.3, pp.384 - 395

ISSN
1084-4309
DOI
10.1145/785411.785417
URI
http://hdl.handle.net/10203/3121
Appears in Collection
EE-Journal Papers(저널논문)
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