Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same 무접합 수직 게이트 트랜지스터와 이의 제조 방법을 가지는 반도체 디바이스

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A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
Assignee
KAIST, SK hynix Inc.
Country
US (United States)
Issue Date
2019-07-23
Application Date
2015-08-12
Application Number
14825030
Registration Date
2019-07-23
Registration Number
10361206
URI
http://hdl.handle.net/10203/264154
Appears in Collection
EE-Patent(특허)
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