Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same무접합 수직 게이트 트랜지스터와 이의 제조 방법을 가지는 반도체 디바이스

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dc.contributor.authorMoon, Jung-Minko
dc.contributor.authorKim, Tae-Kyunko
dc.contributor.authorLee, Seok-Heeko
dc.date.accessioned2019-08-13T09:20:16Z-
dc.date.available2019-08-13T09:20:16Z-
dc.date.issued2019-07-23-
dc.identifier.urihttp://hdl.handle.net/10203/264154-
dc.description.abstractA junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.-
dc.titleSemiconductor device having junctionless vertical gate transistor and method of manufacturing the same-
dc.title.alternative무접합 수직 게이트 트랜지스터와 이의 제조 방법을 가지는 반도체 디바이스-
dc.typePatent-
dc.type.rimsPAT-
dc.contributor.localauthorLee, Seok-Hee-
dc.contributor.nonIdAuthorMoon, Jung-Min-
dc.contributor.nonIdAuthorKim, Tae-Kyun-
dc.contributor.assigneeKAIST, SK hynix Inc.-
dc.identifier.iprsType특허-
dc.identifier.patentApplicationNumber14825030-
dc.identifier.patentRegistrationNumber10361206-
dc.date.application2015-08-12-
dc.date.registration2019-07-23-
dc.publisher.countryUS-
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EE-Patent(특허)
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