Three-Dimensional Integration Approach to High-Density Memory Devices

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dc.contributor.authorKim, Hojungko
dc.contributor.authorJeon, Sanghunko
dc.contributor.authorLee, Myoung-Jaeko
dc.contributor.authorPark, Jaechulko
dc.contributor.authorKang, Sangbeomko
dc.contributor.authorChoi, Hyun-Sikko
dc.contributor.authorPark, Churooko
dc.contributor.authorHwang, Hong-Sunko
dc.contributor.authorKim, Changjungko
dc.contributor.authorShin, Jaikwangko
dc.contributor.authorChung, U-Inko
dc.date.accessioned2018-03-21T02:56:31Z-
dc.date.available2018-03-21T02:56:31Z-
dc.date.created2018-03-07-
dc.date.created2018-03-07-
dc.date.issued2011-11-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.11, pp.3820 - 3828-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/240824-
dc.description.abstractThe three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random accessmemory devices. High-mobility [similar to mu(saturation) of 20 cm(2)/(eV . s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectTHIN-FILM TRANSISTORS-
dc.subjectOXIDE SEMICONDUCTORS-
dc.subjectNONVOLATILE MEMORY-
dc.subjectGRAPHENE-
dc.subjectARRAYS-
dc.titleThree-Dimensional Integration Approach to High-Density Memory Devices-
dc.typeArticle-
dc.identifier.wosid000296099400022-
dc.identifier.scopusid2-s2.0-80054925294-
dc.type.rimsART-
dc.citation.volume58-
dc.citation.issue11-
dc.citation.beginningpage3820-
dc.citation.endingpage3828-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2011.2165286-
dc.contributor.localauthorJeon, Sanghun-
dc.contributor.nonIdAuthorKim, Hojung-
dc.contributor.nonIdAuthorLee, Myoung-Jae-
dc.contributor.nonIdAuthorPark, Jaechul-
dc.contributor.nonIdAuthorKang, Sangbeom-
dc.contributor.nonIdAuthorChoi, Hyun-Sik-
dc.contributor.nonIdAuthorPark, Churoo-
dc.contributor.nonIdAuthorHwang, Hong-Sun-
dc.contributor.nonIdAuthorKim, Changjung-
dc.contributor.nonIdAuthorShin, Jaikwang-
dc.contributor.nonIdAuthorChung, U-In-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorMemory-
dc.subject.keywordAuthoroxide-
dc.subject.keywordAuthorthin-film transistor (TFT)-
dc.subject.keywordAuthor3-D integration-
dc.subject.keywordPlusTHIN-FILM TRANSISTORS-
dc.subject.keywordPlusOXIDE SEMICONDUCTORS-
dc.subject.keywordPlusNONVOLATILE MEMORY-
dc.subject.keywordPlusGRAPHENE-
dc.subject.keywordPlusARRAYS-
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