A low-voltage low-power capacitive-feedback voltage controlled oscillator

Abstract

This paper introduces an LC voltage controlled oscillator (VCO) in current-reuse configuration where transistors are biased in subthreshold region to save power consumption. A capacitive-feedback technique is employed to increase the output swing above the supply voltage and potential ground. Two capacitively source-degenerated negative resistors are employed to reduce the losses of the on-chip inductors resulting in an improved phase noise. The proposed VCO is designed and fabricated in 130 nm CMOS technology. The overall circuit including core VCO and two buffers are biased at low supply voltage of 0.9 V that consumes 490 W. The measured phase noise is - 110 dBc/Hz at 1 MHz offset. A very high FOMT of - 199.3dBc/Hz has been achieved by including tuning range. The chip area is 0.6 x 0.8 mm(2).