Programming schemes for highly reliable TLC NAND flash memory

Abstract

As the NAND flash memory increases its capacity by adopting the multi-level cell technique, the relia-bility degrades significantly, especially in the triple-level cell NAND flash that stores 3 bits per cell. To alleviate the problem and ensure the data integrity, system-level solutions have been addressed. In general, more pow-erful error-correcting codes have been exploited to compensate for the degraded reliability, but the codes are not fully utilized and the area and power overhead becomes larger. In this thesis, new programming methods, braided page programming method and the state remapping method, which can be applied independently to the system to improve the reliability are proposed. The braided page programming method arises from the unbalance nature of bit errors among the data pages stored in the same row of cells and redress the imbal-ance of bit errors. Simulation results prove that it reduces the maximum page error rate by 50% compared to the conventional programming method. The state remapping method is based on the fact that programming lower threshold voltage causes less bit errors than that of the higher threshold voltage. This method analyzes the distribution of the bit patterns and redefines them in the way that the minimum interferences occur. Simu-lation results show that the state remapping method reduces bit error rate by 70% at maximum compared to the conventional method.