Time dependent hot-carrier induced interface state generation in deep submicron LDD nMOSFETs

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The physical mechanism for stress time dependence of hot-carrier induced interface state generation has been investigated by using the lucky-electron model based rate equation and the charge-pumping technique. Both the effective value of critical energy for interface slate generation and the potential barrier for channel hot-electron injection into the gate electrode have been evaluated. The time dependence of interface state generation was formulated with combination of the simple degradation model and the measured barrier heights. It was concluded that the major physical mechanism for self-limiting behavior is the decrement of injected hot-carriers into the oxide due to enhancement of energy-barrier caused by the negative charge build-up at the Si-SiO2 interface.
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Issue Date
1996-03
Language
English
Article Type
Article
Keywords

MOS-TRANSISTORS; FLOATING-GATE; N-MOSFETS; MODEL; DEGRADATION; INJECTION

Citation

SOLID-STATE ELECTRONICS, v.39, no.3, pp.405 - 410

ISSN
0038-1101
URI
http://hdl.handle.net/10203/21246
Appears in Collection
EE-Journal Papers(저널논문)
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