Time dependent hot-carrier induced interface state generation in deep submicron LDD nMOSFETs

Abstract

The physical mechanism for stress time dependence of hot-carrier induced interface state generation has been investigated by using the lucky-electron model based rate equation and the charge-pumping technique. Both the effective value of critical energy for interface slate generation and the potential barrier for channel hot-electron injection into the gate electrode have been evaluated. The time dependence of interface state generation was formulated with combination of the simple degradation model and the measured barrier heights. It was concluded that the major physical mechanism for self-limiting behavior is the decrement of injected hot-carriers into the oxide due to enhancement of energy-barrier caused by the negative charge build-up at the Si-SiO2 interface.