Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

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This brief proposes a new power-efficient Chien search (CS) architecture for parallel Bose-Chaudhuri-Hocquenghem (BCH) codes. For syndrome-based decoding, the CS plays a significant role in finding error locations, but exhaustive computation incurs a huge waste of power consumption. In the proposed architecture, the searching process is decomposed into two steps based on the binary matrix representation. Unlike the first step accessed every cycle, the second step is activated only when the first step is successful, resulting in remarkable power saving. Furthermore, an efficient architecture is presented to avoid the delay increase in critical paths caused by the two-step approach. Experimental results show that the proposed two-step architecture for the BCH (8752, 8192, 40) code saves power consumption by up to 50% compared with the conventional architecture.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-03
Language
English
Article Type
Article
Keywords

NAND FLASH MEMORY; BCH DECODER; HIGH-THROUGHPUT; CODES

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.269 - 273

ISSN
1549-7747
DOI
10.1109/TCSII.2015.2482958
URI
http://hdl.handle.net/10203/208785
Appears in Collection
EE-Journal Papers(저널논문)
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