Achieving lithography-friendly layout typically involves repeated heuristic optimization and lithography simulations, and so is very time-consuming. We propose a light interference map (LIM), in which the value of a particular location represents the extent of potential light interference to nearby patterns if some patterns are relocated (or some new patterns are introduced) to that location. LIM of a single pattern (e.g., contact or via) is obtained through repeated lithography simulations but only once. Superposition of single-pattern LIMs then yields the LIM of an arbitrary layout. LIM opens a possibility of prescriptive layout optimization, which is demonstrated through two example applications: optimizing some contact and via positions and SRAF placement. They are evaluated in 28 nm technology in terms of reduced defect probability.