Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout

Achieving lithography-friendly layout typically involves repeated heuristic optimization and lithography simulations, and so is very time-consuming. We propose a light interference map (LIM), in which the value of a particular location represents the extent of potential light interference to nearby patterns if some patterns are relocated (or some new patterns are introduced) to that location. LIM of a single pattern (e.g., contact or via) is obtained through repeated lithography simulations but only once. Superposition of single-pattern LIMs then yields the LIM of an arbitrary layout. LIM opens a possibility of prescriptive layout optimization, which is demonstrated through two example applications: optimizing some contact and via positions and SRAF placement. They are evaluated in 28 nm technology in terms of reduced defect probability.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-02
Language
English
Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.29, no.1, pp.44 - 49

ISSN
0894-6507
DOI
10.1109/TSM.2015.2512901
URI
http://hdl.handle.net/10203/207429
Appears in Collection
EE-Journal Papers(저널논문)
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