Browse "School of Electrical Engineering(전기및전자공학부)" by Subject inductance
Showing results 1 to 7 of 7
| Embedded microstrip interconnection lines for gigahertz digital circuits Ryu, W; Baik, SH; Kim, H; Kim, J; Sung, MH; Kim, Joungho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.23, no.3, pp.495 - 503, 2000-08 |
| Equivalent Circuit Model for Power Bus Design in Multi-Layer PCBs With Via Arrays Kim, Jingook; Shringarpure, Ketan; Fan, Jun; Kim, Joungho; Drewniak, James L., IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.21, no.2, pp.62 - 64, 2011-02 |
| High-frequency on-chip inductance model Sim, SP; Lee, Kwyro; Yang, CY, IEEE ELECTRON DEVICE LETTERS, v.23, no.12, pp.740 - 742, 2002-12 |
| Inductance Calculations for Plane-Pair Area Fills With Vias in a Power Distribution Network Using a Cavity Model and Partial Inductances Kim, Jingook; Fan, Jun; Ruehli, Albert E.; Kim, Joungho; Drewniak, James L., IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.59, no.8, pp.1909 - 1924, 2011-08 |
| Loop-based inductance extraction and modeling for multiconductor on-chip interconnects Yu, S; Petranovic, DM; Krishnan, S; Lee, Kwyro; Yang, CY, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.53, pp.135 - 145, 2006-01 |
| Modeling of on-chip interconnects inductance and analysis of substrate coupling in cmos integrated circuits = CMOS 집적회로에서의 온칩 인터커넥트 인덕턴스 모델링 및 기판결합 분석link Yu, Sun-Il; 유선일; et al, 한국과학기술원, 2006 |
| Unified model for deep sub-micron on-chip interconnects including non-orthogonal architecture = 비직교형 아키텍쳐를 포함하는 깊은 서브 마이크론 On-chip interconnects 를 위한 통합 모델link Sim, Sang-Pil; 심상필; et al, 한국과학기술원, 2003 |
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