Browse "School of Electrical Engineering(전기및전자공학부)" by Subject DRAM L2 cache

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A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth

Park, SJ; Kim, JS; Woo, R; Lee, SJ; Lee, KM; Yang, TH; Jung, JY; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.37, no.5, pp.612 - 623, 2002-05

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