Browse "School of Electrical Engineering(전기및전자공학부)" by Type Conference
Showing results 18161 to 18180 of 22771
| Time-scale Decomposition and Equivalent Rate Based Marking Yi, Yung; Deb, Supratim; Shakkottai, Sanjay, Institute for Mathematics and its Applications (IMA) Workshop: Measurement, Modeling and Analysis of the Internet, IMA, 2004-01-12 |
| Time-scale separation of nonlinear singularly perturbed discrete systems Park, K.-S.; Lim, Jong-Tae, International Conference on Control, Automation and Systems, ICCAS 2010, pp.892 - 895, ICCAS, 2010-10-27 |
| Time-sclae separation of nonlinear singularly perturbed discrete systems Park, KS; Lim, Jong-Tae, IASTED 2010 , pp.265 - 269, IASTED, 2010 |
| Time-slotted Optical Burst Switching using Centralized Control Choi, JunKyun, OECC/COIN, pp.116 - 117, 2004-07 |
| Time-to-Line Crossing Enhanced End-to-End Autonomous Driving Framework Jung, Chanyoung; Seong, Hyunki; Shim, Hyunchul, 23rd IEEE International Conference on Intelligent Transportation Systems, ITSC 2020, Institute of Electrical and Electronics Engineers Inc., 2020-09-20 |
| Time-varying Causal Flow for Brain Information Flow Measurement Jungsoo Lee; Kim, Dae-Shik, Organization for Human Brain Mapping 2013, Organization for Human Brain Mapping 2013, 2013-06-17 |
| Time-Varying Two-Phase Optimization for Neural Network Learning Myung, Hyun; Kim, Jong-Hwan, Proceedings of the 1994 IEEE International Conference on Neural Networks. Part 1 (of 7), pp.4559 - 4562, ., 1994-06-27 |
| Timed Compiled-Code Functional Simulation of Embedded Software for Performance Analysis of SoC Designs Lee , JY; Park, In-Cheol, 휴먼테크, 2002 |
| Timed compiled-code simulation of embedded software for performance analysis of SOC design Lee, J.-Y.; Park, In-Cheol, 39th Annual Design Automation Conference, DAC'02, pp.293 - 298, 2002-06-10 |
| Timed Petri Nets를 이용한 공장 자동화 시스템의 스케쥴링 변증남, 제어계측연구회, 로보틱스 및 자동화연구회 합동학술발표회, pp.65 - 68, 1989 |
| Timing analysis algorithm for clock gated DETFF based circuits 모민영; 김상민; 신영수, 한국반도체학술대회, 한국반도체학회, 2011-02 |
| Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating Oh, C.; Kim, S.; Shin, Youngsoo, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp.59 - 62, 2009-05-18 |
| Timing Error Detector for OQPSK Signal Seong, J; Lee, HyuckJae; Kim, M, 62nd Technology Conference (VTC-2005), pp.1926 - 1929, IEEE, 2005-09 |
| Timing error masking by exploiting operand value locality in SIMD architecture Sim, Jaehyeong; Park, Jun-Seok; Paek, Seung-Wook; Kim, Lee-Sup, 32nd IEEE International Conference on Computer Design, ICCD 2014, pp.90 - 96, IEEE Circuits and Systems Society, 2014-10 |
| Timing optimization in SADP process through wire widening and double via insertion SONG, YOUNGSOO; Jung, Jinwook; HYUN, DAIJOON; Shin, Youngsoo, SPIE Advanced Lithography, SPIE, 2018-02-28 |
| Timing recovery for sampling detectors in digital magnetic recording Moon, Jaekyun, International Conference on Communications, pp.0 - 0, 1996-06-26 |
| Timing sensitivity in discrete-time equalization Moon, Jaekyun, International Magnetics Conference, pp.0 - 0, 1993-04-15 |
| Timing synchronization for MIMO-OFDM WLAN systems Kim T.; Park, Sin Chong, 5th IASTED Asian Conference on Communication Systems and Networks, AsiaCSN 2008, pp.134 - 136, 2008-04-02 |
| Timing yield estimation with clock network correlations by propagating discrete probability distributions Yu, L.-E.; Shin ,C.; Liou, J.-J.; Shin, Youngsoo, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp.63 - 66, 123, 2009-05-18 |
| Timing-aware wire width optimization for SADP process Song, Youngsoo; Shin, Youngsoo, 20th Design, Automation and Test in Europe, DATE 2017, pp.1639 - 1642, Institute of Electrical and Electronics Engineers Inc., 2017-03-27 |
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