High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

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This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm(2).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-05
Language
English
Article Type
Article
Keywords

CHIP

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.5, pp.1183 - 1187

ISSN
1063-8210
DOI
10.1109/TVLSI.2013.2264687
URI
http://hdl.handle.net/10203/189433
Appears in Collection
EE-Journal Papers(저널논문)
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