Simplifying Clock Gating Logic by Matching Factored Forms

Gate-level clock gating starts with a netlist, with partial or no gating applied; some flip-flops are then selected for further gating to reduce the circuit's power consumption, and a gating logic of the smallest possible size must then be synthesized. We show how to do this by factored form matching, in which gating functions in factored forms are matched, as far as possible, with factored forms of the Boolean functions of existing combinational nodes in the circuit; additional gates are then introduced, but only for the portion of gating functions that are not matched. Strong matching identifies matches that are explicitly present in the factored forms, and weak matching seeks matches that are implicit in the logic and thus are more difficult to discover. Factored form matching reduces gating logic by an average of 24%, over a few test circuits, for which Boolean division only achieves an average reduction of 8%.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-06
Language
ENG
Keywords

ALGORITHMS; CIRCUITS

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.6, pp.1338 - 1349

ISSN
1063-8210
DOI
10.1109/TVLSI.2013.2271054
URI
http://hdl.handle.net/10203/189408
Appears in Collection
EE-Journal Papers(저널논문)
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